Technical Field
The present disclosure relates to a circuit for gene-rating a reference voltage under a power supply voltage smaller than 1 V.
Description of the Related Art
FIG. 1 hereof corresponds to FIG. 3 of French patent application 2969328 of Dec. 17, 2010 (B10442). This drawing shows an example of a circuit generating a reference voltage in the order of 0.1 V. This circuit comprises, between two terminals of application of a power supply voltage VDD and ground GND:                a MOS transistor M1 in series with a bipolar transistor Q1, of type NPN, having its emitter on the side of ground GND;        a MOS transistor M2 in series with a bipolar transistor Q2 (of type NPN, having its emitter on the side of ground GND) and with a resistor R1, the emitter of transistor Q2 defining an output terminal of the circuit providing a reference voltage VOUT, transistors M1 and M2 being assembled as a current mirror; and        the power supply terminals of a follower assembly 3.        
The input of the follower assembly is connected to the collector of transistor Q1 and its output is connected by an optional resistor R2 to the base of transistor Q2. A resistive dividing bridge formed of resistors R3 and R4 in series is connected between the output terminal of follower assembly 3 and ground GND. The midpoint of this dividing bridge is connected to the base of transistor Q1. Resistor R4 is connected between the base of transistor Q1 and ground GND.
Due to the current mirror formed of MOS transistors M1 and M2, transistors Q1 and Q2 receive the same collector current.
As indicated by the above-mentioned French patent application, reference voltage VOUT can be written as follows, neglecting base current ib2 of transistor Q2:VOUT=VBE1 *(R4/R3)+(kT/q)*In(p2|1),  (1)where VBE1 designates the base-emitter voltage of transistor Q1, k designates Boltzmann's constant, q designate the electron charge, T designates the temperature in Kelvin, and In(p2|1) designates the natural logarithm of surface ratio p2|1 between transistors Q1 and Q2 (p2|1 being greater than 1).
Follower assembly 3 is formed of a current source 4 and of a MOS transistor M3. The gate of transistor M3 corresponds to the input of follower assembly 3 and the source of MOS transistor M3 corresponds to the output of follower assembly 3. The follower assembly has the voltage present on its input follow on its output and delivers the current necessary to drive the bases of transistors Q1 and Q2 and for resistor R4. This circuit has an infinite input impedance, and no current flows through the gate of MOS transistor M3.
The base currents of transistors Q1 and Q2 are equal (due to transistors Ml and M2 assembled as a current mirror). Resistor R2 is added to cancel the effect of the base currents on the reference voltage. The compensation will be optimal if the values of resistances R2 and R3 are equal.
Resistor R1 sets the current in the two branches of the assembly. Power supply voltage VDD can be written as:VDD=VOUT+VBE2+R2*ib2+V4,   (2)where VOUT is the reference voltage generated by circuit, VBE2 is the base-emitter voltage of transistor Q2, and V4 is the voltage drop across current source 4.
In practice, in current integrated circuit technologies, the base-emitter voltage of a bipolar transistor is in the order of 0.8 V and the drain-source voltage of a MOS transistor at saturation is in the order of 0.1 V. If a reference voltage VOUT of 0.1 V is desired to be generated, formula (2) thus provides VDD=0.1+0.8+0.1=1 V, neglecting term R2*ib2, which is much smaller than 0.1 V.
FIG. 2 hereof corresponds to FIG. 2 of U.S. Pat. No. 7,408,400. This drawing shows an example of a circuit generating a reference voltage in the order of 0.1 V. This circuit comprises, between two terminals of application of a power supply voltage VDD and ground GND:                a current source 11 generating a current I1 in series with a bipolar transistor Q3, of type NPN;        a current source 13 generating a current I2 in series with a bipolar transistor Q4, of type NPN;        a current source 15 generating the same current I1 as current source 11 in series with a bipolar transistor Q5, of type NPN, and with a resistor R7, the base of transistor Q5 being connected to the collector of transistor Q4; and        a bipolar transistor Q6, of type NPN, in series with a current source 17, the base of transistor Q6 being connected to the collector of transistor Q5 and the emitter of transistor Q6 being connected to the base of transistor Q4.        
Resistor R5 is connected between the base of transistor Q3 and ground GND. A resistor R6 is connected between the collector of transistor Q4 and the base of transistor Q3. A bipolar transistor Q7 is connected between terminal VDD and the emitter of transistor Q5. The base of transistor Q7 is connected to the collector of transistor Q3. The junction point of the emitters of transistors Q5 and Q7 forms output VOUT of the circuit.
Transistors Q3 and Q5 receive a same collector current Ii. As indicated by the above-mentioned US patent, reference voltage VOUT can be written as follows:VOUT=VBE3*(R6/R5)+(kT/q)*In(p5|3),   (3)where VBE3 designates the base-emitter voltage of transistor Q3, k, q, and T have been previously defined, and p5|3 designates the surface ratio between transistors Q3 and Q5 (p5|3 being greater than 1).
Power supply voltage VDD can be written as:VDD=VOUT+VBE7+V11,   (4)where VOUT is the reference voltage generated by circuit, VBE7 is the base-emitter voltage of transistor Q7, and V11 is the voltage drop across current source 11.
In practice, in current integrated circuit technologies, the base-emitter voltage of a bipolar transistor is in the order of 0.8 V and the drain-source voltage of a MOS transistor at saturation is in the order of 0.1 V. If a reference voltage VOUT of 0.1 V is desired to be generated, formula (4) thus provides VDD=0.1+0.8+0.1=1 V.
The power supply voltages of the circuits of FIGS. 1 and 2 are greater than or equal to 1 V.
Further, in the circuits of FIGS. 1 and 2, if voltage VOUT is desired to be increased by 1 V, the power supply voltage should increase by 1 V.
Recent circuits in CMOS technology operate under power supply voltages smaller than or equal to 1 V. The circuits of FIGS. 1 and 2 can thus not be used since they require a power supply voltage greater than 1 V.